A simple introduction to make file
Note: To see my entire list of tutorials click here.
Before we begin to learn how to make a "make file", we should under why it is needed and the background
Background
Skip backgroundWhen you type
gcc file.cor
cc file.cthe following happens
1. Compiler stage: All C language code in the .c file is converted into a lower-level language called Assembly language; making .s files.
2. Assembler stage: The assembly language code made by the previous stage is then converted into object code which are fragments of code which the computer understands directly. An object code file ends with .o.
3. Linker stage: The final stage in compiling a program involves linking the object code to code libraries which contain certain "built-in" functions, such as printf. This stage produces an executable program, which is named a.out by default.
Now lets consider compiling multiple files
When your program becomes very large, it makes sense to divide your source code into separate easily-manageable .c files. The figure above demonstrates the compiling of a program made up of two .c files and a single common.h file. The command is as follows:
gcc green.c blue.cNow you can see that the linker needs to combine multiple .o objects. The 'o' files are first generated and then they are combined in the next step. the 'o' file green.c can be produced by specifying the -c option as follows
gcc -c green.cDo the same for blue.c. Now you can produce the executable by
gcc green.o blue.oEnough of the introduction... Lets look at a real makefile
Sample makefile
Consider the above dependency graph.
you would normally compile this as
gcc -c data.c gcc -c io.c gcc -c main.c gcc data.o io.o main.owhich will produce a.out file
Now you have to repeat the above steps when each of the .c or .h files are changed.
Assume that data.c contains the function which you want to make as a library
sample data.c file
include "data.h" //You should include data.h //welcome functions definition void welcome() { printf("Welcome to my blog http://aravind-sr.blogspot.in \n"); } //other functions
Note that the data.h file must be included
sample data.h file
extern void welcome(); //the keyword extern is must //other declarations
Note that all function declaration should contain the keyword extern
we will create a make file as follows. Create a file named Makefile in the same directory. The contents of the file is as follows
#introduction to make file project1: data.o main.o io.o gcc data.o main.o io.o -o project1 data.o: data.c data.h gcc -c data.c main.o: data.h io.h main.c gcc -c main.c io.o: io.h io.c gcc -c io.c'#' represent the comment.
Every line is of the from
target : source file(s)
command (must be preceded by a tab)
meaning, which all files (source) are needed for the target (this is the dependency). Followed by the action to be done. If you are confused read the below.
Lets assume that we modified data.c or data.h. data.o is dependent on these files. This is exactly represented by third line of the program (including comment). Now what action should we do? We should re-compile the data.c to produce new data.o. This is represented by the fourth line.
To run the make file you should type "make". When you type make the following happens
1. It checks whether the main.o, or io.o, or data.o needs to be updated.
2. If any of the three needs updated it will run that target.
3. Finally it will make the whole project.
Assume that we modified data.c. Now when we type make, the control to project1. From there it goes to main.o, io.o, and data.o. From data.o it knows that it is dependent on data.c and since its modified that command will be executed. Now it will re-compile the project1. So the output will be
gcc -c data.c gcc data.o main.o io.o -o project1This is just an introduction to make file. Please click here to go to the next level, where compilation of specific targets, variables, shortcuts,multiple targets etc will be explained
For advance tutorial click here.
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